Data may be transferred to and from a memory in a number of ways. A memory (e.g., DRAM) may be provided with a memory clock at a predetermined frequency to operate the memory. A random access memory cycle may be used to store or retrieve data from a randomly selected location in a memory. In this instance, the term "random" means that any memory address within the memory may be selected in a non-sequential fashion. Typically, a random access memory cycle may require six to nine memory clock cycles to execute, as the address of the memory location to be accesses must be latched and data then transferred to or from that memory location. The number of memory clock cycles for a random access memory cycle may depend on memory type.
A memory may also be accessed in other modes, for example page mode. In page mode, a number of sequential memory addresses may be accessed in sequence. A first random access memory cycle may be executed to access data from a first location in the memory. Subsequent cycles may then be executed simply by incrementing the address of the first random access memory cycle. The first random access memory cycle may require six or more memory clock cycles to execute, however, subsequent page mode cycles may require fewer memory clock cycles, for example, two.
Thus, the use of page mode cycles may significantly reduce the amount of time needed to transfer data to and from a memory, which conversely increases the capacity to transfer data, over time, to and from a memory. The data rate to and from a memory may be referred to as data bandwidth. The greater the data bandwidth, the greater the data flow rate capacity of a memory and accompanying I/O system.
One problem may occur when transferring data using page mode to and from a memory. As the name implies, page mode accesses data written to a single page, or series of addresses in the memory. If the end of a page is reached (i.e., the end of a range of addresses), a random access memory cycle may be required to access the first address of the next page of memory. Such an event may be referred to as a page miss or page break. The occurrence of a random access memory cycle in a stream of page mode memory cycles may interrupt data flow and/or reduce the data bandwidth of the memory and accompanying I/O system.
One technique for reducing the impact of page misses on the I/O system is to provide a very large FIFO at the input and output of the memory. A larger FIFO may reduce the number of memory clock cycles required to transfer a given amount of data, and thus partially compensate for the additional memory clock cycles required when a page miss occurs. While such a technique may be useful is reducing the impact of page misses on data flow, such large FIFOs may be costly and complex and may require a large amount of space in a semiconductor circuit.
Normally, the first cycle which fills a given FIFO in a system with multiple FIFOs connected to a DRAM is a random cycle. Subsequent cycles to and from the same FIFO may be paged if no page miss occurs. A large FIFO allows to make better use of the initial random cycle, but the impact of a non-aligned page miss is always the same. An extra number of memory clock cycles are needed to transfer the same amount of data.
For example, in a worse case, a random memory cycle may take a total of R memory clock cycles to execute, for example where R=9. A page mode cycle may take P memory clock cycles to execute, for example, where P=2. Thus, the number of additional memory clock cycles required when a page miss occurs is R-P or 7 cycles.
As a further example, a four stage FIFO will be compared with an eight stage FIFO. To execute eight aligned memory accesses for an four stage FIFO, a total of 2.times.(R+3P) memory clock cycles are required. For P=2 and R=7 (typical values) a total of 26 memory clock cycles may be required. To execute the same eight aligned memory accesses for an eight stage FIFO, a total of R+7P cycles may be required, or 21 memory clock cycles. Thus, in general, data may be transferred to or from a larger FIFO using fewer memory clock cycles than in a smaller FIFO.
However, for either sized FIFO, the impact of a page miss may introduce an equal number of additional memory clock cycles. If one page miss occurs during eight memory accesses for a four stage FIFO, a total of (2R+2P)+(R+3P) memory clock cycles are required. For P=2 and R=7 (typical values) a total of 31 memory clock cycles may be required. To execute the same eight memory accesses with one page miss for an eight stage FIFO, a total of 2R+6P cycles would be required, or 26 memory clock cycles. Thus, in either scenario, an additional five (R-P, where R=7 and P=2) memory clock cycles are required for each page miss which occurs.
For video display applications, data may be stored as pixel information in a memory, with each scan line of an image comprising a number of pixels (e.g., 600, 800, 1024). Note that if memory accesses are sequential only one page miss per scan line may occur if a page represents 512 accesses (512 addresses per page), each dword per access represents two pixels at 16 bit per pixel (bpp) resolution or less. For 24 or 32 bpp, more than one page miss may occur in one scan line.
Multimedia computers or PCs may be used to generate graphic graphics, text, video and signals. Of the four types of signals, video may be the most difficult to process in a computer, as the requirements for memory bandwidth and memory capacity are great.
Video controllers are known in the art to generate a television image on a computer video display. Such controllers may comprise, for example, a television tuner and signal generator connected to the output (analog) portion of a controller such as a VGA controller. While such systems may allow a computer monitor to be used as a television display, it may be difficult to integrate the television image with other displays (graphics, text or the like) in a true multimedia format.
In order to achieve high quality live action or full motion video (hereinafter "video") at least 15 or 16 bpp color resolution may be required (32K or 64K colors). High quality computer graphics are generally on the order of eight bpp, whereas texts modes may comprise four bpp. It is cost efficient to combine eight bpp graphics with 16 bpp or 15 bpp video (e.g., CD-ROM video playback). For 32 bit wide DRAMS, running 16 bpp graphics and 16 bpp video may lead to reduced performance and high cost due to the need for at least 2 MB of display memory. Combining 8 bpp graphics with 16 bpp video, however, may be achieved with 1 MB of display memory.
Thus, it remains a requirement in the art to generate a video display in a "window" within a graphics or text image on a computer display. One technique for generating such a video window is to provide an input port in a video controller to receive and digitize an input video image (or use a digitized video image) and store the image in display memory for processing with other graphical or text information. A display memory may be provided to store a predetermined amount of video data in order to compensate for the different data rates of the input data source and the output display.
For example, one frame of video data may be stored in display memory, which then may be referred to as a frame buffer. However, in order to provide realistic live action or full motion video, such a technique may exceed the memory bandwidth limitations of a conventional video controller. It may be possible to provide high speed memories, line or frame buffers and the like in an attempt to optimize memory bandwidth of conventional controllers. However, high speed memories are relatively costly and may not be suited for some applications (e.g., portable computer). Further, high speed memories and large buffers add additional complexity and cost to a video controller.